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PRELIMINARY
CY28437
Clock Generator for Intel Grantsdale Chipset
Features
* Compliant to Intel CK410 * Supports Intel Prescott and Tejas CPU * Selectable CPU frequencies * Differential CPU clock pairs * 100 MHz differential SRC clocks * 96 MHz differential dot clock * 48 MHz USB clocks * 33 MHz PCI clock * Dynamic Frequency Control CPU x2 SRC x8 PCI x8 REF x2 DOT96 x1 USB x2 * Dial-A-Frequency * Watchdog timer * Two Independent Overclocking PLLs * Low-voltage frequency select input * I2C support with readback capabilities * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 56-pin SSOP and TSSOP packages
Block Diagram
Xin Xout
Pin Configuration
VDD_RE F RE F
14.318MHz Crystal PLL Reference
IREF VDD_CPU CPUT CPUC
CPU PLL
FS_[E:A]
Divider
VDD_SRC SRCT SRCC
SRC PLL
Divider
VDD_SRC
SATA PLL
Divider
SRCT4_SATA SRCC4_SATA
VDD_48Mhz
FIX PLL
Divider
DOT96T DOT96C VDD_48
VTTPWR_GD#/PD
USB48 VDD_PCI PCI
VDD_PCI VSS_PCI DF2/PCI3 *FS_E/PCI4 PCI5 VSS_PCI VDD_PCI **DF_EN/PCIF0 **SRESET_EN/PCIF1 VTT_PWRGD#/PD VDD_48 **FS_A/USB48_0 VSS_48 DOT96T DOT96C *FS_B/USB48_1 SRCT0 SRCC0 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRCT4_SATA SRCC4_SATA VDD_SRC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PCI2/DF1 PCI1/DF0 PCI0/SRESET# REF1/**FS_C REF0/**FS_D VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA SRCT7 SRCC7 VDD_SRC SRCT6 SRCC6 SRCT5 SRCC5 VSS_SRC
DF_EN
DF[2:0]
VDD_PCI
* Indicates internal pull-up ** Indicates internal pull-down
CY28437
Dynamic Frequency Watchdog Timer
PCIF
SDATA SCLK
I2C Logic
SRESET#
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 22
www.SpectraLinear.com
CY28437
Pin Description
Pin No. 1,7 2,6 4 5 8 Name VDD_PCI VSS_PCI FS_E/PCI4 PCI DF_EN/PCIF0 Type PWR GND 3.3V power supply for outputs. Ground for outputs. Description
I/O, SE, 3.3V-tolerant input for CPU frequency selection/33-MHz clock. PU Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. O, SE 33 MHz clocks. I/O, SE 3.3V LVTTL input to Enable DF pin/33-MHz Output. PD 1 = Enable, 0 = Disable. Intel Type-5 output buffer
9 10
SRESET_EN/PCIF I/O, PD, 3.3V LVTTL input to enable Watchdog/33-MHz clocks. 1 SE 1 = Enable, 0 = Disable VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C, FS_D, and FSE inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). 3.3V power supply for outputs.
11 12 13 14,15 16
VDD_48 FS_A/USB48_0 VSS_48 DOT96T, DOT96C FS_B/USB48_1
PWR
I/O, PD, 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output. SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. GND Ground for outputs. O, DIF Fixed 96-MHz clock output. I/O, PU, 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output. SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. O, DIF Differential serial reference clocks. Outputs have overclocking capability.
17,18,19,20, SRCT/C 22,23,24,25, 31,30,33,32, 35,36 21,28,34 26,27 29 37 38 39 42 45 46 47 48 49 50 51 52 53 VDD_SRC SRC4_SATAT, SRC4_SATAC VSS_SRC VDDA VSSA IREF VDD_CPU VSS_CPU SCLK SDATA VDD_REF XOUT XIN VSS_REF FS_D/REF0 FS_C/REF1
PWR
3.3V power supply for outputs.
O, DIF Differential serial reference clock. Recommended output for SATA. GND PWR GND I PWR GND I I/O PWR I GND Ground for outputs. 3.3V power supply for PLL. Ground for PLL. A precision resistor is attached to this pin, which is connected to the internal current reference. 3.3V power supply for outputs. Ground for outputs. SMBus-compatible SCLOCK. SMBus-compatible SDATA. 3.3V power supply for outputs. 14.318 MHz crystal input. Ground for outputs.
44,43,41,40 CPUT/C
O, DIF Differential CPU clock outputs.
O, SE 14.318 MHz crystal output.
I/O, SE, 3.3V-tolerant input for CPU frequency selection/Reference clock. PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I/O, SE, 3.3V-tolerant input for CPU frequency selection/Reference clock. PD Selects test mode if pulled to VIHFS_C when VTT_PWRGD# is asserted LOW. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications. O PU 33 MHz clocks/3.3V LVTTL output for Watchdog reset. When configured as SRESET# output this output becomes open drain type with a high (>100k ) internal pull-up resistor.
54
PCI0/SRESET#
3,55,56
DF/PCI
I/O, SE 3.3V LVTTL input for Dynamic Frequency/33-MHz clocks output.
Rev 1.0, November 20, 2006
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CY28437
Frequency Select Pins (FS_[A:E])
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and FS_E inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, FS_C, FS_D, and FS_E input values. For all logic levels of FS_A, FS_B, FS_C, FS_D, and FS_E, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C, FS_D, and FS_E transitions will be ignored, except in test mode. FS_C is a three-level input, when sampled at a voltage greater than 2.1V by VTTPWRGD#, the device will enter test mode as selected by the voltage level on the FS_B input.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Input Conditions FS_D FS_C FS_B FS_A
Output Frequency CPU SRC SRC M CPU PLL CPU M CPU N CPU N SRC PLL SRC N SRC N divider (not DEFAULT allowable Gear divider DEFA ULT allowable Gear Constants range for Constants changeable range for by user) DAF DAF (G)
FSEL_3
FSEL_2
FSEL_1
FSEL_0
(MHz)
(MHz)
0 0 0 0 0 0 0 1 1 1 1 1 1 1 X X
1 0 0 0 0 1 1 1 0 0 0 0 1 1 HIGH HIGH
0 0 1 1 0 0 1 0 0 1 1 0 0 1 LOW HIGH
1 1 1 0 0 0 0 1 1 1 0 0 0 0 X X
100 133.3333333 166.6666667 200 266.6666667 333.3333333 400 100.952381 133.968254 167 200.952381 266.6666667 334 400.6451613 Tristate REF/N
100 100 100 100 100 100 100 100 100 100 100 100 100 100 Tristate REF/N
30 40 60 60 80 120 120 30 40 60 60 80 120 120 Tristate REF/N
60 60 63 60 60 63 60 63 63 60 63 60 60 62 Tristate REF/N
200 200 175 200 200 175 200 212 211 167 211 200 167 207 Tristate REF/N
200 - 250 200 - 250 175 - 262 200 - 250 200 - 250 175 - 262 200 - 250 212 - 262 211 - 262 167 - 250 211 - 262 200 - 250 167 - 250 207 - 258 Tristate REF/N
30 30 30 30 30 30 30 30 30 30 30 30 30 30
60 60 60 60 60 60 60 60 60 60 60 60 60 60
200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 167 - 266 200 167 - 266
Figure 1. CPU and SRC Frequency Select Tables
Rev 1.0, November 20, 2006
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CY28437
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the Table 1. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Description Bit 1 8:2 9 10 18:11 19 20 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Byte Read Protocol Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Stop Block Read Protocol Description
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CY28437
Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 28 29 Stop Description Acknowledge from slave Bit 27:21 28 29 37:30 38 39 Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop Byte Read Protocol Description Slave address - 7 bits
Control Registers
Byte 0: Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name SRC[T/C]7 SRC[T/C]6 SRC[T/C]5 SRC[T/C]4_SATA SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 SRC[T/C]0 Description SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4_SATA Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 0 1 1 0 Name PCIF0 DOT96[T/C] USB_0 REF RESERVED CPU[T/C]1 CPU[T/C]0 CPU PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT96[T/C]MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled USB_0 MHz Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled RESERVED, Set = 0 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on Description
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CY28437
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 RESERVED PCIF1 PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled RESERVED, Set = 1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC[T/C]7 SRC[T/C]6 SRC[T/C]5 SRC[T/C]4_SATA SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 SRC[T/C]0 Description Allow control of SRC[T/C]7 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]6 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]5 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]4_SATA with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]3 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]0 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup HW 0 0 0 0 1 1 1 Name FS_E DOT96 RESERVED PCIF1 PCIF0 RESERVED RESERVED RESERVED Description FS_E Reflects the value of the FS_E pin sampled on power-up. 0 = FS_E was LOW during VTT_PWRGD# assertion. DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state RESERVED, Set = 0 Allow control of PCIF1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of PCIF0 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED, Set = 1 RESERVED, Set = 1 RESERVED, Set = 1
Rev 1.0, November 20, 2006
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CY28437
Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC Description SRC Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP# asserted RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 SRC PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted RESERVED, Set = 0 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted
6 5 4 3 2 1 0
0 0 0 0 0 0 0
RESERVED RESERVED RESERVED SRC[7:0] RESERVED CPU[T/C]1 CPU[T/C]0
Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 HW 1 1 Name TEST_SEL TEST_MODE FS_D REF0 REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode, FS_D reflects the value of the FS_D pin sampled on power-up. 0 = FS_D was LOW during VTT_PWRGD# assertion REF Output Drive Strength 0 = High, 1 = Low Description
PCI, PCIF and SRC clock SW PCI_STP# Function outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert to free running When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. FS_C FS_B FS_A FS_C Reflects the value of the FS_C pin sampled on power-up 0 = FS_C was low during VTT_PWRGD# assertion FS_B Reflects the value of the FS_B pin sampled on power-up 0 = FS_B was low during VTT_PWRGD# assertion FS_A Reflects the value of the FS_A pin sampled on power-up 0 = FS_A was low during VTT_PWRGD# assertion
2 1 0
HW HW HW
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
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CY28437
Byte 8: Control Register 8 Bit 7 @Pup 0 Name CPU_SS Description Spread Selection for CPU PLL 0: -0.5% (peak to peak) 1: -1.0% (peak to peak) Spread Selection for CPU PLL 0: Down spread 1: Center spread SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Spread Selection for SRC PLL 0: -0.5% (peak to peak) 1: -1.0% (peak to peak) RESERVED, Set = 0 48-MHz Output Drive Strength 0 = 2x, 1 = 1x 33-MHz Output Drive Strength 0 = 2x, 1 = 1x RESERVED, Set = 0
6
0
CPU_DWN_SS
5 4
0 0
SRC_SS_OFF SRC_SS
3 2 1 0
0 1 1 0
RESERVED USB PCI RESERVED
Byte 9: Control Register 9 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name DF_Limit2 DF_Limit1 DF_Limit0 DF_EN FSEL_D FSEL_C FSEL_B FSEL_A Dynamic Frequency Enable 0 = Disable, 1 = Enable SW Frequency selection bits. See Table 1. Description Dynamic Frequency Max threshold. These three bits will set the max allowed CPU frequency for Dynamic Frequency
Byte 10: Control Register 10 Bit 7 @Pup 0 Name Recovery_Frequency Description This bit allows selection of the frequency setting that the clock will be restored to once the system is rebooted 0: Use HW settings, 1: Recovery N[8:0] Timer_SEL selects the WD reset function at SRESET pin when WD time out. 0 = Reset and Reload Recovery_Frequency 1 = Only Reset Time_Scale allows selection of WD time scale 0 = 294 ms 1 = 2.34 s WD_Alarm is set to "1" when the watchdog times out. It is reset to "0" when the system clears the WD_TIMER time stamp. Watchdog timer time stamp selection 000: Reserved (test mode) 001: 1 * Time_Scale 010: 2 * Time_Scale 011: 3 * Time_Scale 100: 4 * Time_Scale 101: 5 * Time_Scale 110: 6 * Time_Scale 111: 7 * Time_Scale
6
0
Timer_SEL
5 4 3 2 1
1 0 0 0 0
Time_Scale WD_Alarm WD_TIMER2 WD_TIMER1 WD_TIMER0
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CY28437
Byte 10: Control Register 10 (continued) Bit 0 @Pup 0 Name WD_EN Description Watchdog timer enable, when the bit is asserted, Watchdog timer is triggered and time stamp of WD_Timer is loaded 0 = Disable, 1 = Enable
Byte 11: Control Register 11 Bit 7 @Pup 0 Name CPU_DAF_N7 Description If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used.
6 5 4 3 2 1 0
0 0 0 0 0 0 0
CPU_DAF_N6 CPU_DAF_N5 CPU_DAF_N4 CPU_DAF_N3 CPU_DAF_N2 CPU_DAF_N1 CPU_DAF_N0
Byte 12: Control Register 12 Bit 7 @Pup 0 Name CPU_DAF_N8 Description If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used.
6 5 4 3 2 1 0
0 0 0 0 0 0 0
CPU_DAF_M6 CPU_DAF_M5 CPU_DAF_M4 CPU_DAF_M3 CPU_DAF_M2 CPU_DAF_M1 CPU_DAF_M0
Byte 13: Control Register 13 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC_N7 SRC_N6 SRC_N5 SRC_N4 SRC_N3 SRC_N2 SRC_N1 SRC_N0 SRC Dial-A-Frequency Bit N7 SRC Dial-A-Frequency Bit N6 SRC Dial-A-Frequency Bit N5 SRC Dial-A-Frequency Bit N4 SRC Dial-A-Frequency Bit N3 SRC Dial-A-Frequency Bit N2 SRC Dial-A-Frequency Bit N1 SRC Dial-A-Frequency Bit N0 Description
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CY28437
Byte 14: Control Register 14 Bit 7 6 @Pup 0 0 Name SRC_N8 SW_RESET SRC Dial-A-Frequency Bit N8 Software Reset. When set the device will assert a reset signal on SRESET# upon completion of the block/word/byte write that set it. After asserting and deasserting the SRESET# this bit will self clear (set to 0). The SRESET# pin must be enabled by latching SRESET#_EN on VTT_PRWGD# to utilize this feature. FS_Override 0 = Select operating frequency by FS(D:A) input pins 1 = Select operating frequency by FSEL_(3:0) settings Smooth switch select 0: Select CPU_PLL 1: Select SRC_PLL RESERVED, Set = 0 RESERVED, Set = 0 Free running 33-MHz Output Drive Strength 0 = 2x, 1 = 1x Watchdog Recovery Bit Description
5
0
FS_[E:A]
4
0
SMSW_SEL
3 2 1 0
0 0 1 0
RESERVED RESERVED PCIF Recovery_N8
Byte 15: Control Register 15 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Recovery N7 Recovery N6 Recovery N5 Recovery N4 Recovery N3 Recovery N2 Recovery N1 Recovery N0 Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Description
Byte 16: Control Register 16 Bit 7 6 5 @Pup 1 1 0 Name REF1 USB48_1 SRC_FREQ_SEL REF1 Output Enable 0 = Disable, 1 = Enable USB48_1 Output Enable 0 = Disable, 1 = Enable SRC Frequency selection 0: SRC frequency is selected via the FSE pin 1: SRC frequency is initially set to 167 MHz. RESERVED, Set = 0 SATA PLL Spread Spectrum Enable 0 = Spread off, 1 = Spread on Programmable SRC frequency enable 0 = Disabled, 1 = Enabled. Programmable CPU frequency enable 0 = Disabled, 1 = Enabled. Description
4 3 2 1 0
0 0 0 0 1
RESERVED SRC_SATA Prog_SRC_EN Prog_CPU_EN
Watchdog Autorecovery Watchdog Autorecovery Mode 0 = Disable (Manual), 1= Enable (Auto)
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CY28437
Table 4. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm
The CY28437 requires a parallel resonance crystal. Substituting a series resonance crystal will cause the CY28437 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
Clock Chip
Ci1
Ci2 Pin 3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 2 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
X1 X2
Cs1
Cs2 Trace 2.8pF
XTAL Ce1
Ce2
Trim 33pF
Figure 3. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
Figure 2. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
=
1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2
)
CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.)
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CY28437
Dynamic Frequency
Dynamic Frequency - Dynamic Frequency (DF) is a technique to increase the CPU frequency dynamically from any starting value. The user selects the starting point, either by HW, FSEL, or DAF, then enables DF. After that, DF will dynamically change as determined by the value on the DF[2:0] pins. DF/PCI Pin - These PCI pins incorporate dual functions, either DF or PCI. The function is selected by the DF_EN pin. When used as DF, these three pins will map to eight entries that correspond to different "N" values for Dynamic Frequency. Below is a table that list the combinations along with the increase in "N". DOC[2:0] 000 001 010 011 100 101 110 111 DOC N value Original Frequency +2 +6 +10 +14 +18 +30 +40 0 (0000) The allowable values for N are detailed in the frequency select table in Figure 1. CPU_DAF_M - There are 7 bits (for 128 values) to linearly change the CPU frequency (limited by VCO range). Default = 0. The allowable values for M are detailed in the frequency select table in Figure 1. SRC_DAF Enable - This bit enables SRC DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the SRC_DAF_N register. Note: the SRC_DAF_N register must contain valid values before SRC_DAF is set. Default = 0 (No DAF) SRC_DAF_N - There are 9 bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0 (0000) The allowable values for N are detailed in the frequency select table in Figure 1. Recovery - The recovery mechanism during CPU DAF when the system locks up and the Watchdog timer is enabled is determined by the "Watchdog Recovery Mode" and "Watchdog Auto recovery Enable" bits. The possible recovery methods are: (A) Auto, (B) Manual (by Recovery N), (C) HW, and (D) No recovery--just send reset signal. There is no recovery mode for SRC Dial-a-frequency.
Software Frequency Select
This mode allows the user to select the CPU output frequencies using the Software Frequency select bits in the SMBUS register. FSEL - There are 4 bits (for 16 combinations) to select predetermined CPU frequencies from a table. The table selections are detailed in Figure 1. FS_Override - This bit allows the CPU frequency to be selected from HW or FSEL settings. By default, this bit is not set and the CPU frequency is selected by HW. When this bit is set, the CPU frequency is selected by the FSEL bits. Default =0 Recovery - The recovery mechanism during FSEL when the system locks up is determined by the "Watchdog Recovery Mode" and "Watchdog Auto recovery Enable" bits. The only possible recovery method is from the Hardware Settings. Auto recovery or manual recovery can cause a wrong output frequency because the output divider may have changed with the selected CPU frequency and these recovery methods will not recover the original output divider setting.
DF_EN bit - This bit enables the DF mode. By default, it is not set. When set, the operating frequency is determined by DF[2:0] pins. Default = 0, (No DF) DF_Limit bit - There are three bits that allow the user to set an upper limit to prevent CPU runaway. In the event that the user uses DAF with DF, this feature will provide some safeguard so the CPU won't burn up.
Dial-A-Frequency (CPU and SRC)
This feature allows the user to overclock their system by slowly stepping up the CPU or SRC frequency. When the programmable output frequency feature is enabled, the CPU and SRC frequencies are determined by the following equation Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M "N" and "M" are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. "G" stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A]. See Figure 1 for the Gear Constant for each Frequency selection. The PCI Express only allows user control of the N register, the M value is fixed and documented in Figure 1. In this mode, the user writes the desired N and M value into the DAF I2C registers. The user cannot change only the M value and must change both the M and the N values at the same time, if they require a change to the M value. The user may change only the N value if required. Associated Register bits CPU_DAF Enable - This bit enables CPU DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note: the CPU_DAF_N and M register must contain valid values before CPU_DAF is set. Default = 0 (No DAF) CPU_DAF_N - There are 9 bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = Rev 1.0, November 20, 2006
Smooth Switching
The device contains one smooth switch circuit that is shared by the CPU PLL and SRC PLL. The smooth switch circuit ensures that when the output frequency changes by overclocking, the transition from the old frequency to the new frequency is a slow, smooth transition containing no glitches. The rate of change of output frequency when using the smooth switch circuit is less than 1 MHz/0.667 s. The frequency overshoot and undershoot will be less than 2%. The Smooth Switch circuit can be assigned to either PLL via register byte 14 bit 4. By default the smooth switch circuit is assigned to the CPU PLL. Either PLL can still be overclocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches.
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It is not recommended to enable overclocking and change the N values of both PLLs in the same SMBUS block write. Watchdog Autorecovery Enable - This bit is set by default and the recovered values are automatically written into the "Watchdog Recovery Register" and reloaded by the watchdog function. When this bit is not set, the user is allowed to write to the "Watchdog Recovery Register". The value stored in the "Watchdog Recovery Register" will be used for recovery. Default = 1, Autorecovery. Watchdog Recovery Register - This is a nine-bit register to store the Watchdog N recovery value. This value can be written by the Auto recovery or User depending on the state of the "Watchdog Auto recovery Enable bit".
Watchdog Timer
The Watchdog timer is used in the system in conjunction with overclocking. It is used to provide a reset to a system that has hung up due to overclocking the CPU and the Front side bus. The Watchdog is enabled by the user and if the system completes its checkpoints, the system will clear the timer. However, when the timer runs out, there will be a reset pulse generated on the SRESET# pin for 20 ms that is used to reset the system. When the Watchdog is enabled (WD_EN = 1) the Watchdog timer will start counting down from a value of Watchdog_timer * time scale. If the Watchdog timer reaches 0 before the WD_EN bit is cleared then it will assert the SRESET# signal and set the Watchdog Alarm bit to 1. To use the Watchdog the SRESET# pin must be enabled by SRESET_EN pin being sampled LOW by VTTPWRGD# assertion during system boot-up. At any point during the Watchdog timer countdown, if the time stamp or Watchdog timer bits are changed, the timer will reset and start counting down from the new value. After the Reset pulse, the Watchdog will stay inactive until either: 1. A new time stamp or Watchdog timer value is loaded. 2. The WD_EN bit is cleared and then set again. Watchdog Register Bits The following register bits are associated with the Watchdog timer: Watchdog Enable - This bit (by default) is not set, which disables the Watchdog. When set, the Watchdog is enabled. Also, when there is a transition from LOW to HIGH, the timer reloads. Default = 0, disable Watchdog Timer - There are three bits (for seven combinations) to select the timer value. Default = 000. The Value '000' is a reserved test mode. Watchdog Alarm - This bit is a flag and when it is set, it indicates that the timer has expired. This bit is not set by default. When the bit is set, the user is allowed to clear. Default = 0. Watchdog Time Scale - This bit selects the multiplier. When this bit is not set, the multiplier will be 250 ms. When set (by default), the multiplier will be 3s. Default = 1. Watchdog Reset Mode - This selects the Watchdog reset mode. When this bit is not set (by default), the Watchdog will send a reset pulse and reload the recovery frequency depends on Watchdog Recovery Mode setting. When set, it just send a reset pulse. Default = 0, Reset & Recover Frequency. Watchdog Recovery Mode - This bit selects the location to recover from. One option is to recover from the HW settings (already stored in SMBUS registers for readback capability) and the second is to recover from a register called "Recovery N". Default = 0 (Recover from the HW setting).
Watchdog Recovery Modes
There are three operating modes that require Watchdog recovery. The modes are Dial-A-Frequency (DAF), Dynamic Clocking (DF), or Frequency Select. There are 4 different recovery modes: The following section lists the operating mode and the recovery mode associated with it. Recover to Hardware M,N, O When this recovery mode is selected, in the event of a watchdog timeout, the original M, N, and O values that were latched by the HW FSEL pins at chip boot-up should be reloaded. Autorecovery When this recovery mode is selected, in the event of a Watchdog timeout, the M and N values stored in the Recovery M and N registers should be reloaded. The current values of M and N will be latched into the internal recovery M and N registers by the WD_EN bit being set. Manual Recovery When this recovery mode is selected, in the event of a Watchdog timeout, the N value as programmed by the user in the N recovery register, and the M value that is stored in the Recovery M register (not accessible by the user) should be restored. The current M value should be latched M recovery register by the WD_EN bit being set. No Recovery If no recovery mode is selected, in the event of a watchdog time out, the device should just assert the SRESET# and keep the current values of M and N
Software Reset
Software reset is a reset function which is used to send out a pulse from the SRESET# pin. It is controlled by the SW_RESET enable register bit. Upon completion of the byte/word/block write in which the SW_RESET bit was set, the device will send a RESET pulse on the SRESET# pin. The duration of the SRESET# pulse should be the same as the duration of the SRESET# pulse after a Watchdog timer time out. After the SRESET# pulse is asserted the SW_RESET bit should be automatically cleared by the device.
Rev 1.0, November 20, 2006
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CY28437
PD (Power-down) Clarification The VTT_PWRGD#/PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must be held HIGH or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within four clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to `0', the clock
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C
output are held with "Diff clock" pin driven high at 2 x Iref, and "Diff clock#" tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to "1", then both the "Diff clock" and the "Diff clock#" are tri-state. Note the example below shows CPUT = 133 MHz and PD drive mode = `1' for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, 200, 266, 333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 s after asserting Vtt_PwrGd#. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip's internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up.
PCI, 33 MHz REF
Figure 4. Power-down Assertion Timing Waveform
Tstable <1.8ms
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF
Tdrive_PWRDN# <300 S, >200mV
Figure 5. Power-down Deassertion Timing Waveform
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S1 S2 VTT_PWRGD# = Low
Delay >0.25mS
VDD_A = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD_A = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 6. Clock Generator Power-up/Run State Diagram
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Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional Mil-STD-883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 150 70 150 20 60 - Unit V V VDC C C C C/W C/W V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter All VDDs VILI2C VIHI2C VIL_FS VIH_FS VILFS_C VIMFS_C VIH FS_C VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPD3.3V IPT3.3V Description 3.3V Operating Voltage Input Low Voltage Input High Voltage FS_[A:B,D:E] Input Low Voltage FS_[A:B,D:E] Input High Voltage FS_C Low Range FS_C Mid Range FS_C High Range 3.3V Input Low Voltage 3.3V Input High Voltage Input Low Leakage Current Input High Leakage Current 3.3V Output Low Voltage 3.3V Output High Voltage High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current Power-down Supply Current At max. load and freq. per Figure 9 PD asserted, Outputs Driven PD asserted, Outputs Tri-state Except internal pull-up resistors, 0 < VIN < VDD Except internal pull-down resistors, 0 < VIN < VDD IOL = 1 mA IOH = -1 mA 3.3 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS - 0.3 0.7 0 0.7 2.1 VSS - 0.3 2.0 -5 - - 2.4 -10 3 3 - 0.7VDD 0 - - - Max. 3.465 1.0 - 0.35 VDD + 0.5 0.35 1.7 VDD 0.8 VDD + 0.3 - 5 0.4 - 10 5 5 7 VDD 0.3VDD 500 70 2 Unit V V V V V V V V V V A A V V A pF pF nH V V mA mA mA
Rev 1.0, November 20, 2006
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CY28437
AC Electrical Specifications
Parameter Crystal TDC Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1- s duration Over 150 ms Min. 47.5 Max. 52.5 Unit %
TPERIOD T R / TF TCCJ LACC
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy
69.841 - - - 45 9.997001 7.497751 5.998201 4.998500 3.748875 2.999100 2.499250 9.997001 7.497751 5.998201 4.998500 3.748875 2.999100 2.499250 9.912001 7.412751 5.913201 4.913500 3.663875 2.914100 2.414250 9.912001 7.412751 5.913201 4.913500 3.663875 2.914100 2.414250 -
71.0 10.0 500 300 55 10.00300 7.502251 6.001801 5.001500 3.751125 3.000900 2.500750 10.05327 7.539950 6.031960 5.026634 3.769975 3.015980 2.513317 10.08800 7.587251 6.086801 5.086500 3.836125 3.085900 2.585750 10.13827 7.624950 6.116960 5.111634 3.854975 3.100980 2.598317 100
ns ns ps ppm % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps
CPU at 0.7V (SSC refers to -0.5% spread spectrum) TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period 166-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period 266-MHz CPUT and CPUC Period 333-MHz CPUT and CPUC Period 400-MHz CPUT and CPUC Period Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX
100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 266-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 333-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 400-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 100-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 133-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 166-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 200-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 266-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 333-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 400-MHz CPUT and CPUC Absolute period Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 133-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 166-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 200-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 266-MHz CPUT and CPU C Absolute period, SSC TPERIODSSAbs 333-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 400-MHz CPUT and CPUC Absolute period, SSC TSKEW CPU0 to CPU1
Rev 1.0, November 20, 2006
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CY28437
AC Electrical Specifications (continued)
Parameter TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB SRC TDC TPERIOD TPERIODSS TPERIODAbs Description CPUT/C Cycle to Cycle Jitter Long Term accuracy CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage SRCT and SRCC Duty Cycle 100-MHz SRCT and SRCC Period 100-MHz SRCT and SRCC Absolute Period See Figure 9. Measure SE Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Math averages Figure 9 Math averages Figure 9 Condition Measured at crossing point VOX Measured using frequency counter over 0.15 seconds. Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Min. - - 130 - - - 660 -150 250 - -0.3 - 45 9.997001 9.997001 9.872001 9.872001 - - - 130 - - - Math averages Figure 9 Math averages Figure 9 660 -150 250 - -0.3 See Figure 9. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V - 45 29.99100 29.9910 29.49100 29.49100 12.0 12.0 Max. 65 300 700 29 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 10.00300 10.05327 10.12800 10.17827 250 125 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 30.00900 30.15980 30.50900 30.65980 - - Unit ps ppm ps % ps ps mV mV mV V V V % ns ns ns ns ps ps ppm ps % ps ps mV mV mV V V V % ns ns ns ns ns ns
100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC TSKEW TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB PCI/PCIF TDC TPERIOD TPERIODSS TPERIODAbs THIGH TLOW PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Disabled PCIF/PCI Period PCIF and PCI high time PCIF and PCI low time Any SRCT/C to SRCT/C Clock Skew SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Times Rise/Fall Matching Rise TimeVariation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
Rev 1.0, November 20, 2006
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CY28437
AC Electrical Specifications (continued)
Parameter Edge Rate Edge Rate TSKEW TCCJ DOT TDC TPERIOD TPERIODAbs TCCJ LACC TLTJ Description Rising edge rate Falling edge rate Any PCI clock to Any PCI clock Skew PCIF and PCI Cycle to Cycle Jitter DOT96T and DOT96C Duty Cycle DOT96T and DOT96C Period DOT96T/C Cycle to Cycle Jitter DOT96T/C Long Term Accuracy Long Term jitter Condition Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measurement taken from cross point VOX@1 s Measurement taken from cross point VOX@10 s T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB USB TDC TPERIOD TPERIODAbs THIGH TLOW Edge Rate Edge Rate TCCJ TLTJ DOT96T and DOT96C Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Duty Cycle Period Absolute Period USB high time USB low time Rising edge rate Falling edge rate Cycle to Cycle Jitter Long Term jitter See Figure 9. Measure SE Measurement at 1.5V In High Drive mode Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement taken from cross point VOX@1 s Measurement taken from cross point VOX@10 s Measurement taken from cross point VOX@125 s
REF TDC
Min. 0.85 0.85 - - 45 10.41354 10.16354 - - - - 130 - - -
Max. 6.0 6.0 500 550 55 10.41979 10.66979 250 100 700 700 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 20.83542 21.18542 10.5 10.5 2.4 2.4 200 700 700 700
Unit V/ns V/ns ps ps % ns ns ps ppm ps ps ps % ps ps mV mV mV V V V % ns ns ns ns V/ns V/ns ps ps ps ps
DOT96T and DOT96C Absolute Period Measured at crossing point VOX
Determined as a fraction of *(TR - TF)/(TR + TF)
Math averages Figure 9 Math averages Figure 9
660 -150 250 - -0.3 - 45 20.83125 20.48125 8.094 7.694 0.52 0.52 - - - -
REF Duty Cycle REF Period REF Absolute Period
Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V
45 69.8203 68.82033
55 69.8622 70.86224
% ns ns
TPERIOD TPERIODAbs
Rev 1.0, November 20, 2006
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CY28437
AC Electrical Specifications (continued)
Parameter T R / TF Edge Rate Edge Rate TCCJ TSTABLE Description REF Rise and Fall Times Rising edge rate Falling edge rate REF Cycle to Cycle Jitter Clock Stabilization from Power-up Condition Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measurement at 1.5V Min. 0.5 1.0 1.0 - - Max. 2.0 4.0 4.0 1000 1.8 Unit V/ns V/ns V/ns ps ms
ENABLE/DISABLE and SET-UP
Test and Measurement Set-up
For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals.
PCI/ USB
Measurement Point
5pF
Measurement Point
5pF
REF
Measurement Point
5pF
Figure 7. Single-ended Load Configuration
Measurement Point
5pF
PCI/ USB
Measurement Point
5pF
Measurement Point
5pF
REF
Measurement Point
5pF
Measurement Point
5pF
Figure 8. Single-ended Load Configuration HIGH DRIVE OPTION
Rev 1.0, November 20, 2006
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CY28437
For Differential CPU, SRC and DOT96 Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs.
M e a s u re m e n t P o in t
2pF
D if f e r e n t ia l
CPUT SRCT DO T96T
CPUC SRCC DO T96C
M e a s u re m e n t P o in t
2pF
IR E F
Figure 9. 0.7V Single-ended Load Configuration
3 .3 V s ig n a l s
T DC
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
TR
TF
Figure 10. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number Lead-free CY28437OXC CY28437OXCT CY28437ZXC CY28437ZXCT 56-pin SSOP 56-pin SSOP - Tape and Reel 56-pin TSSOP 56-pin TSSOP - Tape and Reel Commercial, 0 to 85 C Commercial, 0 to 85 C Commercial, 0 to 85 C Commercial, 0 to 85 C Package Type Product Flow
Rev 1.0, November 20, 2006
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CY28437
Package Diagrams
56-Lead Shrunk Small Outline Package O56
.020
28 1
0.395 0.420 0.292 0.299
DIMENSIONS IN INCHES MIN. MAX.
29
56
0.720 0.730 SEATING PLANE 0.088 0.092 0.095 0.110
GAUGE PLANE
.010
0.005 0.010
0.110 0.025 BSC 0.008 0.0135 0.008 0.016 0-8
0.024 0.040
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547] 14.097[0.555]
1.100[0.043] MAX.
GAUGE PLANE 0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008]
0.170[0.006] 0.279[0.011]
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
Page 22 of 22

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